1. Field of the Invention
The present invention relates generally to plating methods employed for forming microelectronic fabrications. More particularly, the present invention relates to selective plating methods employed for forming microelectronic fabrications.
2. Description of the Related Art
Microelectronic fabrications are formed from microelectronic substrates over which are formed patterned microelectronic conductor layers which are separated by microelectronic dielectric layers.
As microelectronic fabrication integration levels have increased and patterned microelectronic conductor layer dimensions have decreased, it has become increasingly common in the art of microelectronic fabrication to employ selective plating methods for forming within microelectronic fabrications selectively plated patterned microelectronic conductor layers within microelectronic fabrications.
Selective plating methods are desirable in the art of microelectronic fabrication for forming selectively plated patterned microelectronic conductor layers within microelectronic fabrications insofar as selective plating methods are generally more economical than other methods which may be employed for forming patterned microelectronic conductor layers within microelectronic fabrications, where such other methods may include but are not limited to chemical vapor deposition (CVD) methods and physical vapor deposition (PVD) methods which may be employed for forming patterned microelectronic conductor layers within microelectronic fabrications.
While selective plating methods are thus desirable in the art of microelectronic fabrication for forming selectively plated patterned microelectronic conductor layers within microelectronic fabrications, selective electroplating plating methods in particular are nonetheless also not entirely without problems in the art of microelectronic fabrication for forming selectively plated patterned microelectronic conductor layers within microelectronic fabrications. In that regard, it is known in the art of microelectronic fabrication that selective electroplating methods when employed for forming selectively plated patterned microelectronic conductor layers within microelectronic fabrications often provide non-uniform selectively plated patterned microelectronic conductor layers, in particular with respect to thickness non-uniformity of the selectively plated patterned microelectronic conductor layers.
It is thus desirable in the art of microelectronic fabrication to provide selective plating methods through which there may be formed within microelectronic fabrications selectively plated patterned microelectronic conductor layers with enhanced uniformity, and in particular with enhanced thickness uniformity.
It is towards the foregoing object that the present invention is directed.
Various methods and apparatus have been disclosed in the art of microelectronic fabrication for forming microelectronic conductor layers, and in particular plated microelectronic conductor layers, with desirable properties within the art of microelectronic fabrication.
For example, Yee et al., in U.S. Pat. No. 5,135,636, disclose an electroplating method and an electroplating apparatus which may be employed for forming over a microelectronic substrate employed within a microelectronic fabrication a plated microelectronic conductor layer with enhanced thickness uniformity. To realize the foregoing object, the electroplating method and the electroplating apparatus employ when forming the plated microelectronic conductor layer over the microelectronic substrate employed within the microelectronic fabrication a metal electroplating cathode ring separated from, surrounding and electrically connected to the microelectronic substrate when plating simultaneously over both the microelectronic substrate and the metal electroplating cathode ring the plated microelectronic conductor layer.
In addition, Reynolds, in U.S. Pat. No. 5,932,077, discloses a plating apparatus which may be employed for plating, with enhanced manufacturing efficiency, a microelectronic conductor layer over a microelectronic substrate employed within a microelectronic fabrication while employing a plating method. To realize the foregoing object, the plating apparatus employs a plating chamber having a door upon which may be fixtured the microelectronic substrate over which is formed the microelectronic conductor layer while employing the plating method.
Finally, Uzoh, in U.S. Pat. No. 6,056,869, discloses a method and an apparatus which may be employed for providing a residue free conductor layer formed over a microelectronic substrate employed within a microelectronic fabrication. To realize the foregoing result the method and the apparatus comprise a deplating method and a deplating apparatus by which undesirable conductor layer residues are deplated from edge surfaces and backside surfaces of the microelectronic substrate employed within the microelectronic fabrication.
Desirable in the art of microelectronic fabrication are additional methods and materials which may be employed for forming, with enhanced thickness uniformity, plated microelectronic conductor layers within microelectronic fabrications.
It is towards the foregoing object that the present invention is directed.
A first object of the present invention is to provide a plating method for forming a plated microelectronic conductor layer within a microelectronic fabrication.
A second object of the present invention is to provide a plating method in accord with the first object of the present invention, wherein the plated microelectronic conductor layer is formed with enhanced thickness uniformity.
A third object of the present invention is to provide a plating method in accord with the first object of the present invention and the second object of the present invention, wherein the plating method is readily commercially implemented.
In accord with the objects of the present invention, there is provided in a first instance by the present invention a method for forming a patterned photoresist layer. To practice the method of the present invention, there is first provided a substrate. There is then formed over the substrate a blanket photoresist layer formed of a negative photoresist material. There is then photoexposed the blanket photoresist layer to form a photoexposed blanket photoresist layer while employing a photoexposure apparatus which employs an annular edge ring exclusion apparatus positioned over an annular edge ring of the blanket photoresist layer and the substrate. Finally, there is then developed the photoexposed blanket photoresist layer to form a patterned photoresist layer having an annular edge ring excluded over the annular edge ring of the substrate.
In further detail, under circumstances where the substrate has formed thereover a blanket electroplating seed layer prior to forming thereover the blanket photoresist layer, and further wherein the blanket photoresist layer is formed upon the blanket electroplating seed layer and the blanket photoresist layer is simultaneously photoexposed and developed to provide in addition to an annular edge ring excluded over an annular edge ring of the blanket electroplating seed layer a series of exposed interior portions of the blanket electroplating seed layer upon which it is desired to form a series of selectively electroplated patterned conductor layers while employing an electroplating method which employs an annular cathode electrode ring contact to the annular edge ring of the blanket electroplating seed layer, the series of selectively electroplated patterned conductor layers formed while employing the electroplating method is formed with enhanced thickness uniformity since the series of selectively electroplated patterned conductor layers formed while employing the electroplating method may be formed with an enhanced electrical contact of the annular cathode electrode ring to the annular edge ring of the blanket electroplating seed layer.
The present invention provides a plating method for forming a plated microelectronic conductor layer within a microelectronic fabrication, wherein the plated microelectronic conductor layer is formed with enhanced thickness uniformity.
The present invention realizes the foregoing object in a first instance by employing within a photoexposure apparatus employed for photoexposing a blanket photoresist layer formed over a substrate to provide a photoexposed blanket photoresist layer formed over the substrate an annular edge exclusion apparatus positioned over an annular edge ring of the blanket photoresist layer and the substrate, such that when the photoexposed blanket photoresist layer is developed to form a patterned photoresist layer, the patterned photoresist layer is formed with an annular edge ring excluded over the annular edge ring of the substrate. Further, by forming in accord with the present invention an annular edge ring of a patterned photoresist layer excluded over a blanket electroplating seed layer there may be formed an optimal electrical contact of an annular cathode electrode ring to the blanket electroplating seed layer and thus provide enhanced thickness uniformity of a series of patterned conductor layers formed employing an electroplating method in conjunction with the blanket electroplating seed layer.
The method of the present invention is readily commercially implemented. The present invention employs methods and materials as are generally known within the art of microelectronic fabrication or readily adapted to the art of microelectronic fabrication but employed within the context of specific limitations to provide the present invention. Since it is thus a series of specific limitations of methods and materials which provides at least in part the present invention, rather than the existence of methods and materials which provides the present invention, the method of the present invention is readily commercially implemented.